High speed computers require densely packaged integrated circuit. Such packages must be highly reliable and they must provide for physically supporting, interconnecting, and for cooling the integrated circuits.
Factors that must be considered in the design of high density packages for integrated circuits include: (a) the number of circuits per chip, (b) the number of chip to module interconnections, (c) the chip power requirements and (d) the number of input-output connections provided by the package. Modern digital computers require a packaging technology that provides a relatively large number of integrated circuit chips in a single package and which provides for literally thousands of I-O connections to the package. Furthermore, the I-O pins must be pluggable so that the package can be removed from a circuit board on which the package is mounted. One modern packaging system used in commercially available high speed digital computers is shown in several articles published during 1981 and 1982 in the IBM Journal of Research and Development, Volume 25 Number 5, Volume 26 Number 1, and Volume 26 Number 3. In particular see:
(a) An article entitled "Electronic Packaging Evolution in IBM", IBM Journal of Research and Development, Volume 25, Number 5 pages 617-629, Sept. 1981 by D. P. Seraphim and I. Feinberg,
(b) An article entitled "Advanced Printed Circuit Board Design for High Performance Computer Applications", IBM Journal of Research and Development, Volume 26 Number 3, pages 297-305, May 1982, by R. F. Bonner, J. A. Asselta, and F. W. Haining, and
(c) An article entitled "Thermal Conduction Module: A High Performance Multilayer Ceramic Package", IBM Journal of Research and Development, Volume 26 number 3 Number 1, pages 30-36, Jan. 1982 by A. J. Blodgett and D. R. Barbour.
In the module shown in the above articles, power is supplied to the module through the same type of pins that carry signals to the module. This has at least two disadvantages. First, the design of the pins and the pin connectors must take into account both the requirements of signal connections and the requirements of power connections, thereby limiting the design choices available. Second, any pins used for power connections reduces the number of pins available for signal connections. A large variety of other packages for integrated circuits are known in the art. For example, U.S. Pat. No. 3,846,734 (Pauza) et al. shows an example of a dual in-line circuit package. U.S. Pat. No. 3,808,506 (Lang) shows a package with contact pads on both sides of a block. U.S. Pat. No. 3,614,541 (Farrand) shows a board with connectors on multiple sides. U.S. Pat. No. 4,137,559 (Reuting) shows a package with connectors on multiple sides of the package. Other references of general interest which show the state of the art include U.S. Pat. Nos. 3,634,602 (Bruck), 3,934,959 (Gilissen), 3,795,037 (Luttmer), 3,496,283 (Andrasfay), 3,107,414 (Sterling), 3,105,868 (Feigin) et al., 3,029,495 (Doctor), and 3,643,135 (Devore) et al.
There are known circuit packaging technologies where the power connections are separated from the signal connections. Furthermore, as shown in the previously referenced articles in the IBM Journal of Research and Development the use of multilayer ceramic (generally termed MLC) substrates in electronic packages is well known. However, none of the art shows or suggests a structure which has a frame made of MLC and where the power connectors are separated from the signal connectors as with the present invention. Furthermore, none of the known circuit packaging technologies provide the density, reliability and number of I-O connections provided by the present invention.
The present invention also provides an improved edge connector for a multilayer ceramic substrate which is not shown or suggested by the prior art.